As nonvolatile semiconductor memory devices, a three-dimensional memory cell structure of a floating-gate electrode type and using side walls of a floating gate electrode as capacitance has been proposed. Memory cells of a floating-gate electrode type have an inter poly dielectric (IPD) and a control gate on a floating gate electrode.
In a process of manufacturing such memory cells, an upper part of the floating gate electrode is exposed by processing a shallow trench isolation (STI) structure and performing after-treatment by a chemical solution. In this processing, the floating gate electrode is exposed to the atmosphere, and thus oxygen adheres to the surface of the floating gate electrode, and an oxide film is formed on the surface.
The oxide film formed as described above has low capacity to resist pressure, and low insulation. In addition, since the oxide film is located in an interface between the floating gate electrode and the IPD, it can be an element which determines the writing characteristic of the device. Specifically, forming the IPD on the oxide film deteriorates the writing characteristic. More specifically, when a high electric field is applied in writing, a leakage current of the IPD increases, and decrease in the writing speed is caused.